The MASTECS consortium will present a paper titled 'Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSo' authored by Alejandro Serrano (BSC), Juan M Reina (BSC), Enrico Mezzetti (BSC & Maspatechnologies), Jaume Abella (BSC & Maspatechnologies), and Francisco J Cazorla (BSC & Maspatechnologies) in a session chaired by Benny Akesson (University of Amsterdam / TNO) at the 33rd Euromicro Conference on Real-Time Systems.
The paper explores the interference co-running tasks generated on each other’s timing behavior to be addressed before Multi-Processor System-on-Chip (MPSoCs) are fully embraced in critical systems like those deployed in avionics and automotive domains. The suggested solution to this challenge are modern MPSoCs like the Xilinx Zynq UltraScale+ incorporate hardware Quality of Service (QoS) mechanisms that can help controlling contention among tasks. Therefore, the authors perform to their knowledge the first qualitative and quantitative analysis of the distributed QoS mechanisms in the UltraScale+ MPSoC. It is empirically derived the QoS information not covered by the technical documentation and show limitations and benefits of the available QoS support. To that end, the authors use a case study building on neural network kernels commonly used in autonomous systems in different real-time domains.
Moreover, Francisco J Cazorla, MASTECS coordinator, will chair Session 1: Hardware Predictability on July 5, 2021 from 15:00 to 16:00 (CEST).
Find more information about this event here.
