The MASTECS technical article titled "Ensuring software timing behavior in critical multicore-based embedded systems" was published on the Embedded platform on 20 July 2020.
First, the article delves into how MASTECS will mature the Multicore Analysis (MTA) technology, support its use for certification of avionics systems and offer state of the art tools that are capable of analyzing the timing of software on multicore platforms, with strong focus on applicable safety standards and emerging certification requirements.
Subsequently, the article focuses on the use of micro-benchmarks in interference analysis that are supported with a task contention model that provides early estimates of the contention delay tasks. A 7-steps design methodology was developed to fully understand the impact of interference.
Finally, the early and late design stages are explained into detail giving special attention to how the 7-step design process is only one part of a wider multicore verification methodology to then conclude that expertise cannot be automated and how experts in hardware and software need to closely collaborate with each other.
Read the full article here